Expand description
This module represents the time during a simulation.
Time is made up of a cycle count and a phase.
Structsยง
- Clock
- State representing a clock.
- Clock
Delay - Future returned by the clock to manage advancing time using async functions.
- Clock
State - Shared state between futures using a Clock and the Clock itself.
- Clock
Tick - ClockTick structure for representing a number of Clock ticks and a phase.
- Task
Waker