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Crate gwr_models

Crate gwr_models 

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§gwr-models

Models are the constructed from components and resources and run by the gwr_engine.

The gwr_models library provides a collection of connectable models to be used when building larger models and simulations. The following is a brief and not exhaustive list of the models provided.

§Frames

Many systems are based on frames (packets) of different forms.

§Memory Access

Memory traffic is represented with MemoryAccess, which carries routing, access type, payload size, and protocol overhead.

§Ethernet Frame

The EthernetFrame represents a frame that looks like the one defined in the standards.

§Flow Controlled Pipeline

A flow controlled pipeline represents a low-level hardware component which can be used to moved data in a system. It comprises a buffer that will hold data received from the sender and a credit-based mechanism for ensuring the buffer doesn’t overflow.

Interfaces: rx: input port, tx: output port

The EthernetLink is effectively a bi-directional set of connections that have similar properties to a connection over an Ethernet link.

Interfaces: rx_a, rx_b : input ports, tx_a, tx_b: output ports

§Memory

A model of a memory to handle read/write accesses.

Interfaces: rx: input port, tx: output port

§Cache

A basic model of a n-way set associative cache.

Interfaces:

§Ring Node

A model of a node that can sit in a ring communication topology.

Interfaces:

§Fabric

A model of a two-dimensional interconnect fabric. It is provided in both functional and routed implementations that provide the same interfaces but trade off model accuracy vs run-time performance.

**Interfaces:**gwr-

§Testing

Models can be tested using the build_model_harness! macro. This wraps a model with a simple test harness that drives and expects objects that implement the AccessMemory trait. The model harness uses the same harness DSL and generated API as build_component_harness!, but uses MemoryTxn to check objects coming out of the model.

MemoryTxn lets tests match only the memory access fields that matter for a scenario. For example, this test harness checks that a Memory model produces a read response for the expected destination address, while ignoring fields that are not specified:

mod memory_harness {
    use std::rc::Rc;

    use gwr_engine::test_helpers::start_test;
    use gwr_models::build_model_harness;
    use gwr_models::memory::memory_access::MemoryAccess;
    use gwr_models::memory::{Memory, MemoryConfig};
    use gwr_models::test_helpers::{MemoryTxn, create_default_memory_map, create_read};

    const DST_ADDR: u64 = 0x80000;
    const SRC_ADDR: u64 = 0x90000;
    const ACCESS_SIZE_BYTES: usize = 64;
    const OVERHEAD_SIZE_BYTES: usize = 8;

    build_model_harness! {
        harness MemoryHarness<T> {
            component: memory: Rc<Memory<T>>,
            rx ports: {
                Rx<T> => rx,
            },
            tx ports: {
                Tx<T> => tx,
            },
        }
    }

    #[test]
    fn model_harness_matches_selected_memory_fields() {
        let mut engine = start_test(file!());
        let clock = engine.default_clock();
        let config = MemoryConfig::new(DST_ADDR, 0x40000, 32, 1);
        let memory = Memory::<MemoryAccess>::new_and_register(
            &engine,
            &clock,
            engine.top(),
            "memory",
            config,
        )
        .unwrap();
        let memory_map = Rc::new(create_default_memory_map());
        let request = create_read(
            engine.top(),
            &memory_map,
            ACCESS_SIZE_BYTES,
            DST_ADDR,
            SRC_ADDR,
            OVERHEAD_SIZE_BYTES,
        );
        let mut harness = MemoryHarness::new(engine, memory);

        harness.run_steps([
            send_rx!(request),
            expect_tx!(MemoryTxn::read_rsp(DST_ADDR)),
        ]);
    }
}

Use the component harness documentation for the shared syntax and execution model.

Modules§

ethernet_frame
The EthernetFrame provides an implementation of a standard Ethernet frame
ethernet_link
Bi-directional link with two ends (a & b).
fabric
Models of fabric interconnects.
fc_pipeline
Flow Controlled Pipeline.
memory
processing_element
A Processing Element (PE) for a simulation.
registers
Control and Status Registers builders.
ring_node
A simple node of a ring.
test_helpers

Macros§

array
Allow the creation of compile-time arrays of state up to 8 elements long without needing the Copy trait to be implemented.
build_model_harness
Builds a simulation test harness for models that implement AccessMemory.
build_register_file
build_register_state
build_register_states
build_register_view

Functions§

log_stats