Expand description
A basic n-way set-associative cache model.
The cache provides no memory ordering guarantees.
TODO: Should cache accesses return an error if they are not cache-line aligned or sized?
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| Device |
----------------------------
| |
| |
----------------------------
| dev_rx dev_tx |
| | ^ |
| | | |
| | delay |
| | | |
| | 0 response |
| +---------> arbiter |
| | ^ |
| delay | 1 |
| | Cache | |
| v | |
| mem_tx mem_rx |
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| |
| |
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| Mem/Bus |
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